1. Field of the Invention
The present invention relates to the manufacture of integrated circuit transistor structures, and more particularly to the use of ion implantation for doping a transistor gate electrode layer.
2. Description of the Related Art
Polysilicon is used extensively for the gate electrode of insulated gate field effect transistors (IGFETs), including use in advanced CMOS technologies. Typically a layer of polysilicon is formed on a gate dielectric layer previously formed on a semiconductor body, such as a substrate. The polysilicon is doped with a P-type or N-type dopant, and etched to form a respective gate electrode for each respective transistor. For a CMOS technology, the polysilicon gate electrode layer may be doped with a P-type dopant in certain regions for use as a gate electrode for a P-channel IGFET, and doped with an N-type dopant in other regions for use as a gate electrode for an N-channel IGFET.
As semiconductor technologies have scaled to ever smaller dimensions, it is desirable to also reduce the thickness of a polysilicon gate layer. Several factors warrant the use of a thinner polysilicon layer to form the gate electrodes. First, a thin polysilicon layer is easier to control the etching necessary to define narrow and controllable features, which become the gate electrodes. The width of the gate electrodes define the electrical length of the IGFET, which is a crucial parameter for transistor performance and operating characteristics. The controllability of the polysilicon etch (i.e., the "critical dimension control" or "CD control") is reduced as thickness is increased. Moreover, a thin polysilicon layer is desirable for formation of narrower spacer structures which are necessary for high performance transistor structures. Since the width of a spacer formed adjacent to a gate electrode is a function of the thickness of the polysilicon layer, thinner polysilicon layers allow narrower spacers. Additionally, a more uniform doping of a dopant is achievable as a polysilicon layer becomes thinner. Lastly, a thinner polysilicon layer reduces the vertical dimensions of the structure, and facilitates planarization issues or metal step coverage concerns.
However, as polysilicon layers become thinner, they become harder to dope using ion-implantation. Modern ion implantation equipment, when used in a production environment, requires an extraction energy from the implant source in the range from 15-25 KeV. An implanter using an energy below this range is usually unable to extract a significant number of ions from the implanter source, and is therefore unable to implant any dopant atoms into the semiconductor work piece. Even when using an acceleration energy as low as possible, the dopant atoms may penetrate through a thin poly layer. This is especially true when implanting boron, which is a relatively light, highly-diffusive atom, into a thin polysilicon layer. The boron may all to easily penetrate through the polysilicon layer and become implanted in either the gate dielectric layer (e.g., a "gate oxide" layer) or even into the channel region of the IGFET disposed below the gate dielectric layer. Such a penetration has disastrous effects on both threshold control of the transistor and on the reliability of the transistor. Phosphorus is used as a frequent N-type dopant, and although heavier than boron, still may exhibit the same penetration effects at slightly different energies or polysilicon layer thicknesses.
Current technology then limits the thickness of a polysilicon layer to a value much thicker than desired, or risk the penetration of dopants, especially boron, into the oxide or channel. What is needed is a production-worthy technique for doping polysilicon layers of ever decreasing thickness without risk of implanting dopants into underlying layers. Without such a technique, the advantages of thin polysilicon layers cannot be easily achieved.